A well-known form of integrator is the Miller integrator. The Miller integrator incorporates an active device, e.g. a transistor amplifier, in order to improve the linearity of the output from a source such as a pulse generator. A capacitance connected between the input and the output of the amplifier results in an apparent increase in the capacitance across the input terminals of the amplifier. With current technology the amplifier is conveniently configured as an operational amplifier.
A Phase Lock Loop (PLL) is a frequently used circuit in communication systems, and is employed, for example, in radio tuning circuits and clock extraction circuits in optical fibre receivers for timing references.
The basic structure of a PLL is shown in FIG. 1. The main components consist of a phase detector 10, a loop filter 12, a voltage controlled oscillator 14 and a feed back loop 16 which typically incorporates a divider 18. The PLL compares an incoming signal, such as a clock signal, with its feedback clock.
The difference between these two signals generates an error signal proportional to the gain of the phase detector, Kd, which error signal is applied to the loop filter. The loop filter typically consists of an active single pole-zero filter such as a typical Miller integrator with a compensating zero, providing both high dc gain, which reduces input phase error (usually the gain of the filter, G is not less than 40 dB) and low frequency bandwidth. The output of this active filter adjusts a Voltage Controlled Oscillator (VCO) or a crystal VCO (VCXO) to lock the output signal to the input signal. The VCO however may have a centre frequency (f.sub.o) at a much higher frequency (depending on system requirements) and a therefore a divide down counter may be placed within the feedback path, which completes the loop.
As with all second order feedback circuits (not just PLL) the PLL has two distinct characteristics
The Natural Frequency, .omega..sub.n =2.pi.f.sub.n =(K.sub.o K.sub.d G/t.sub.1 N).sup.1/2 ; and PA1 the Damping Factor, .zeta.=(1/2.omega.t.sub.1)+(.omega..sub.n t.sub.2 /2) PA1 i) the first (pole) time constant, t.sub.1, would need to be 14.99.times.10.sup.3 sec; and PA1 ii) the second (zero) time constant, t.sub.2, would need to be 21.55 sec ##EQU2## Since t.sub.1 =Cf Rf PA1 t.sub.2 =Cf Rz and PA1 G=-Rf/Rs
These two parameters are determined by, inter alia, the characteristics of the loop filter.
The 3 dB bandwidth of the PLL is known as the Jitter Bandwidth (f.sub.jb) which is defined as: ##EQU1##
To prevent a jitter gain of greater than 0.5 dB; the damping factor, .zeta., needs to be greater than or equal to 1.76.
With the advent of Passive Optical Networks (PON) becoming a means of providing fibre to the home with the ability to allow householders to become interactive (i.e. providing facilities such as video on demand, home shopping etc.) the optical transmitter at the home (outstation) requires very accurate timing information. This timing information can be derived from the down stream source (the broadcast base station transmitter). This timing information is provided to allow the outstation optical transmitter to send data within its designated time slot. The timing source at the base station is provided by a primary PLL which needs to have a jitter bandwidth of no more than, typically, 0.1 Hz, for 50 Mb/s transmission. This jitter bandwidth requires that the natural frequency of the PLL must be in the order of 0.025 Hz.
If a standard Miller integrator of the type shown in FIG. 2 were used to provide a jitter bandwidth of 0.025 Hz while maintaining a damping factor equal to 1.76, then;
Thus, if a standard Miller integrator were to be employed to provide such a stringent PLL jitter bandwidth, the values of the resistors that would be required would be of the order of tens of G.OMEGA.. Resistors of this rating are, however, not be realisable when used with standard sizes of low leakage, non-electrolytic capacitors.
An alternative type of Miller integrator is known from GB2220092B, and an example of such is shown in FIG. 3. This type of circuit has the potential to provide enhanced time constants: whilst this integrator effectively multiplies the value of the integrating resistor by the gain G, the value of R is still required to be of the order of M.OMEGA. which is unrealisable in some practical circuits.